Reconfigurable Neural Net Chip with 32K Connections
نویسندگان
چکیده
We describe a CMOS neural net chip with a reconfigurable network architecture. It contains 32,768 binary, programmable connections arranged in 256 'building block' neurons. Several 'building blocks' can be connected to form long neurons with up to 1024 binary connections or to form neurons with analog connections. Singleor multi-layer networks can be implemented with this chip. We have integrated this chip into a board system together with a digital signal processor and fast memory. This system is currently in use for image processing applications in which the chip extracts features such as edges and corners from binary and gray-level images.
منابع مشابه
D3NOC: Dynamic Data-Driven Network On Chip in Photonic Electronic Hybrids
In this paper we present a reconfigurable hybrid Photonic-Plasmonic Network-on-Chip (NoC) based on the Dynamic Data Driven Application System (DDDAS) paradigm. In DDDAS computations and measurements form a dynamic closed feedback loop in which they tune one another in response to changes in the environment. Our proposed system enables dynamic augmentation of a base electrical mesh topology with...
متن کاملReconfiguration Strategy for FPGA Dependability Characteristics Improvement based on Stochastic Petri Net
This paper shows the impact of the trade-off between reconfigurable and non-reconfigurable parts of the FPGA to the dependability characteristics of the whole design. Stochastic Petri nets have been used to compute reliability and dependability characteristics in a simple FPGA design with dynamically reconfigurable modules. Some parts of the design are not possible or proper to reconfigure dyna...
متن کاملEMBRACE: Emulating Biologically–Inspired Architectures on Hardware
This paper highlights and discusses the current challenges in the implementation of large scale Spiking Neural Networks (SNNs) in hardware. A mixed-mode approach to realising scalable SNNs on a reconfigurable hardware platform is presented. The approach uses compact low power analogue spiking neuron cells, with a weight storage capability, interconnected using Network on Chip (NoC) routers. Res...
متن کاملTowards Dilated Placement of Dynamic NoC Cores
Instead of mapping application task graphs in a compact manner onto reconfigurable devices using a network-on-chip for interconnecting application cores, we propose dilating the mappings as much as the available latencies on critical connections allow. In a dilated mapping, the unused resources between an application’s configured components can be used to provide additional flexibility when the...
متن کاملKeys for Administration of Reconfigurable NoC: Self-Adaptive Network Interface Case Study
The design of recent Systems-on-Chip (SoC) for a large scope of applications, such as telecom and multi-media domains, and in various platform types ranging from dedicated platforms to fully programmable platforms, is mainly constrained by communications. Networks-on-Chip (NoC) have recently emerged as a promising concept to support communication on SoCs providing a solution to connect differen...
متن کامل